Modern-day electronic and optical systems require multiple patterned layers of electrically or optically active materials, sometimes over a relatively large substrate. Electronics such as radio frequency identification (RFID) tags, photovoltaic components, and optical and chemical sensors all require some level of patterning in their electronic circuitry. Flat panel displays, such as liquid crystal displays or electroluminescent displays rely upon accurately patterned sequential layers to form thin-film components of the backplane. These electronic components include capacitors, transistors, and power buses. The usual combination of photolithographic patterning methods and selective etch processes has several shortcomings including high cost, difficulty with large substrates, and complexity of selective etch processes.
In the semiconductor industry there is much interest in the ability to align a material layer to features formed in the substrate or to underlying layers. Sacrificial filler material has been used to fill vias and other recess topography to prevent deposition within the recesses, and as such to limit deposition only to the top surface of the substrate. Similarly, complicated manufacturing schemes have been employed to pattern materials such that it is only present within the recessed areas on substrates having a surface topography.
There is a growing interest in depositing thin-film semiconductors on plastic or flexible substrates, particularly because these supports are more mechanically robust, lighter weight, and allow more economic manufacturing, for example, by allowing roll-to-roll processing. Plastics, however, typically limit device processing to below 200° C. There are many other issues associated with the use of plastic supports when using traditional photolithography during conventional manufacturing, making it difficult to perform alignments of transistor components across typical substrate widths, which can be up to one meter or more. Traditional photolithographic processes and equipment may be seriously impacted by the substrate's maximum process temperature, solvent resistance, dimensional stability, water, and solvent swelling, which are all key parameters where plastic supports are typically inferior to glass.
There is also a growing interest in printed electronics with solution-processed active components such as conductive inks, insulating materials, and organic semiconductors. However, it can be difficult to print active materials in high resolution patterns with good alignment, as well as with good orthogonality. Solutions to aspects of this problem have been suggested such as printing onto surfaces that are pre-patterned with different surface energies to contain the printed ink (for example, see U.S. Pat. No. 7,571,529 to H. Sirringhaus et al.).
Several approaches involving surface topography to pattern thin-films with solution-processed active components have also been described. In U.S. Pat. No. 7,571,529, Sirringhaus et al. describes a surface covered with a thin conductive layer which is divided by solid state embossing into two distinct electrical regions separated by a trench. The topography is thus introduced after the thin-film deposition. They further describe using the trench, or microgroove, to selectively deposit material in the microgroove by means of fluid flowing by capillary forces. Since the fluid flowing along the groove is the active material, the desired properties of the dried film must be compatible with those required for the fluid to flow along the trench or groove.
Other groups have described alternative uses of substrate topography for electronic device fabrication. In U.S. Patent Application Publication 2010/0301337, Rider et al. describes the benefits of trenches, or channels, aligned to each other in formation, and of different depths, for the formation of electronic devices with self-aligned electrodes. Once again, the surface features are used to direct the flow of a fluid, or several fluids, containing the active materials for the device.
In light of the complicated existing processes there is an ongoing need to provide simple manufacturing solutions to patterning thin-films in relationship to the topography of a substrate. There is also an ongoing need to provide techniques capable of processing small device features for electronic components without requiring high resolution alignment, in particular the ability to pattern features at a higher resolution than that of a given printing method is highly desired. These needs exist for all substrates, however there is an additional need to address the added complications associated with using deformable substrates by developing self-aligned processes.